Cerberus: hierarchical DFT rule checker

Author

Knopf, Reinhard ; Trischler, Erwin

Author_Institution

Siemens AG, Munich, West Germany

fYear

1989

fDate

12-14 Apr 1989

Firstpage

58

Lastpage

62

Abstract

The hierarchical design for testability (DFT) rule checker Cerberus has been developed to handle hierarchical circuits supporting a variety of scan structures with different types of scannable storage devices. Cerberus utilizes a general approach to testability rule checking and is part of a computer-aided engineering system to integrate design and test. Cerberus consists of the following components: an extractor to provide a levelized directed graph representation from a circuit netlist, a preprocessor to provide acyclic graphs and for topological sorting of circuit nodes, a rule checker nucleus to perform the DFT verification process hierarchically, and a protocol generator to output the rule-checker results in a user-friendly representation

Keywords

VLSI; automatic testing; circuit CAD; directed graphs; logic testing; ASIC; Cerberus; VLSI; acyclic graphs; automatic testing; computer-aided engineering; design/test integration; hierarchical circuits; hierarchical design for testability; levelized directed graph; preprocessor; protocol generator; scan structures; scannable storage devices; testability rule checking; topological sorting; verification; Circuit testing; Clocks; Computer aided engineering; Delay; Design for testability; Law; Legal factors; Logic; Sequential analysis; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

European Test Conference, 1989., Proceedings of the 1st

Conference_Location

Paris

Print_ISBN

0-8186-1937-6

Type

conf

DOI

10.1109/ETC.1989.36220

Filename

36220