Beyond CMOS scaling

Summary form only given. A key concept in the ULSI roadmap is a miniaturization. As long as this trend does not encounter some intrinsic limitations, one must try to keep up with this concept. 0.1 μm CMOS in the gate level is under optimization in many laboratories and the performance improvement follows this trend. However, intrinsic limitations originate from other factors, such as many intrinsic parasitics, performance fluctuations or power consumption, even if a cost issue is excluded. First, these issues are discussed, based on our experimental results. In fact, one will try to come up with the roadmap to 2010, while one must find an exit for a new paradigm by using other devices, or architectures. Therefore, such a kind of new device is discussed. The important point in the research of new devices is that the base material should be silicon, which will be a unique solution for an assimilation with the current Si ULSI world.