Performance analysis method under process variations

With the shrinking device size, process variations have a growing impact on circuit performance for today´s integrated circuit (IC) technologies. In this paper, a hierarchical modeling for performance analysis is built. A novel parameter reduction method based on CH (Correlation-Hessian matrix) is presented. It accounts for all correlations, from manufacturing process dependence, to high-level analysis to produce more accurate performance predictions. Experimental results indicate that the proposed method achieves high computational efficiency and accuracy.