How to treat transmission line effects when testing high speed devices with a high performance test system

State-of-the-art digital ASICs have even faster clock rates and signal transition times; testing these devices may cause problems regarding delivering the signals to the device under test (DUT) and precisely measuring the response of the DUT. Transmission-line techniques have to be applied to the tester-to-DUT interconnection in order to maintain signal fidelity. The author illustrates how to implement this critical signal path in a high-speed test system to get high-precision timing and level measurements, particularly for CMOS devices. The solution suggested to embed a CMOS device in a transmission-line environment is the resistive divider. The operating principle of the resistive divider is to apply a definable DC load to the DUT. This maintains signal fidelity, as the signal is fed into a parallel terminated system. Therefore no reflections occur