Design and implementation of a hierarchical testable architecture using the boundary scan standard

Author

van Riessen, R.P. ; Kerkhoff, H.G. ; Kloppenburg, A.

Author_Institution

IC-Technol. & Electron. Group, Twente Univ., Enschede, Netherlands

fYear

1989

fDate

12-14 Apr 1989

Firstpage

112

Lastpage

118

Abstract

A standardized and structured test methodology is described which is based on the boundary-scan proposal of JTAG (Joint Test Action Group). The architecture ensures the testability of the hardware from printed-circuit-board level down to integrated-circuit level. In addition, the architecture has the feature of built-in self-test at the IC level. The implementation of the architecture by means of a self-test compiler is discussed. The test hardware for the hierarchically testable architecture at the macro level consists of test interface elements and a macro test processor; these components are examined in detail

Keywords

VLSI; automatic test equipment; automatic testing; computer architecture; integrated circuit testing; printed circuit testing; IC testing; JTAG; PCB testing; automatic testing; boundary scan standard; built-in self-test; hierarchical testable architecture; macro test processor; printed-circuit-board; self-test compiler; standardised test; structured test methodology; test interface elements; Automatic testing; Built-in self-test; Circuit testing; Computer architecture; Electronic equipment testing; Hardware; Integrated circuit testing; Proposals; Standards development; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

European Test Conference, 1989., Proceedings of the 1st

Conference_Location

Paris

Print_ISBN

0-8186-1937-6

Type

conf

DOI

10.1109/ETC.1989.36231

Filename

36231