DocumentCode
2343251
Title
Testing multiple power connections with boundary scan
Author
van de Lagemaat, D.
Author_Institution
Philips Telecommun. & Data Syst., Hilversum
fYear
1989
fDate
12-14 Apr 1989
Firstpage
127
Lastpage
130
Abstract
Boundary-scan techniques for testing multiple power connections on VLSI components are described. Power-connection testing issues during the several stages of a component´s life are considered, including IC design, IC production, PCB design, PCB assembly, and system use. The techniques developed involve the use of a RAM sense amplifier and a flip-flop sensor
Keywords
VLSI; fault location; integrated circuit testing; logic testing; printed circuit testing; production testing; IC design; IC production; PCB assembly; PCB design; RAM sense amplifier; VLSI components; boundary scan; flip-flop sensor; multiple power connections; Assembly; Circuit testing; Clocks; Electronics packaging; Integrated circuit packaging; Integrated circuit technology; Pins; Power supplies; System testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
European Test Conference, 1989., Proceedings of the 1st
Conference_Location
Paris
Print_ISBN
0-8186-1937-6
Type
conf
DOI
10.1109/ETC.1989.36233
Filename
36233
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