EB-testing-pad method and its evaluation by actual devices

Author

Kuji, Norio ; Ishihara, Takako

fYear

2001

fDate

2001

Firstpage

179

Lastpage

184

Abstract

A practical EB-testing-pad method, that enables higher observability of multi-level wiring LSIs without any increase of chip size, has been evaluated by using actual 0.25-μm SIMOX/CMOS devices. First, an 80 k-gate logic LSI with testing pads was developed, and it was proved that observability improves from 17% to 87%. Next, two kinds of gate-chain TEGs (test element groups), one with and one without testing pads were developed to investigate the influence of testing pads on gate delay. It was found that the circuit delay increase due to the pads is very small, less than 4%. It was also found that capacitances from neighboring wires will increase only by at most 2% due to the testing pads. Thus, the testing pad method has been proved to be sufficiently practical as a design method suitable for failure analysis

Keywords

CMOS logic circuits; SIMOX; delay estimation; electron beam testing; failure analysis; integrated circuit layout; integrated circuit reliability; integrated circuit testing; large scale integration; logic testing; observability; 0.25 micron; EB-testing-pad method; LSI chips; LSI layout; SIMOX/CMOS devices; Si; capacitances; failure analysis; gate delay; gate-chain test element groups; logic LSI; multi-level wiring LSIs; multilevel wiring; observability; stacked vias; CMOS logic circuits; Capacitance; Circuit testing; Delay; Large scale integration; Logic devices; Logic testing; Observability; Wires; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2001. Proceedings. 10th Asian

Conference_Location

Kyoto

ISSN

1081-7735

Print_ISBN

0-7695-1378-6

Type

conf

DOI

10.1109/ATS.2001.990278

Filename

990278