An efficient method to identify untestable path delay faults

Several methods to reduce the run time and memory requirements of a procedure used to efficiently identify untestable path delay faults are proposed in this work. Based on the correlation between the conditions required for sensitizing subpaths in the fan-out-free regions of a circuit, equivalence relations between the subpaths are defined. Equivalence relations are used to reduce the number of subpaths considered in the identification of untestable paths. Dynamic pruning of the potential search space for identifying pairs of subpaths that cannot be sensitized together is used to achieve additional speedup. Results on benchmark circuits show the effectiveness of the proposed methods