Mixed level test generation for MOS circuits

Author

Lioy, A.

Author_Institution

Dept. of Autom. & Inf., Polytech. of Torino, Italy

fYear

1989

fDate

12-14 Apr 1989

Firstpage

208

Lastpage

211

Abstract

The authors present a test-generation system for combinational circuits described at mixed gate and switch levels. The circuit under test is hierarchically partitioned into blocks characterized by their I/O function. Only the faulty block is eventually expanded to perform fault injection. The algorithm also exploits dynamic partitioning and adaptive backtrace to speed up the test search. Robust tests for stuck-open faults are derived with the help of a ternary simulation technique. Preliminary results show that on large circuits a saving of an order of magnitude can be expected in CPU time when compared with performance on a flat gate-level implementation

Keywords

CMOS integrated circuits; MOS integrated circuits; VLSI; automatic testing; combinatorial circuits; fault location; integrated circuit testing; integrated logic circuits; logic testing; CMOS; CPU time; I/O function; MOS IC; VLSI; adaptive backtrace; combinational circuits; dynamic partitioning; fault injection; mixed gate; mixed level test generation; stuck-open faults; switch levels; ternary simulation; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Heuristic algorithms; Partitioning algorithms; Robustness; Switches; Switching circuits; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

European Test Conference, 1989., Proceedings of the 1st

Conference_Location

Paris

Print_ISBN

0-8186-1937-6

Type

conf

DOI

10.1109/ETC.1989.36245

Filename

36245