Testability design for PLA-implemented finite state machine

Design-for-testability (DFT) techniques are presented for the finite state machine implemented in programmable logic arrays (PLAs). The proposed techniques are developed from physical, electrical and functional points of view. Within the framework of deterministic test, these DFT techniques make the fault under consideration either unlikely to occur, equivalent to other faults, or more easily testable. They allow a significant reduction in fault locations and in fault models. A detailed example illustrates the proposed techniques, highlighting the improvements. It is shown that specific DFT techniques developed for regular structures allow the automatic generation of easily testable functional blocks. For CMOS PLA, the test sequence is reduced in such a way that the automatic generation of self-testable finite-state machines is possible