DocumentCode
2343593
Title
Thread-aware dynamic shared cache compression in multi-core processors
Author
Xie, Yuejian ; Loh, Gabriel H.
Author_Institution
Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2011
fDate
9-12 Oct. 2011
Firstpage
135
Lastpage
141
Abstract
When a program´s working set exceeds the size of its last-level cache, performance may suffer due to the resulting off-chip memory accesses. Cache compression can increase the effective cache size and therefore reduce misses, but compression also introduces access latency because cache lines need to be decompressed before using. Cache compression can help some applications but hurt others, depending on the working set of the currently running program and the potential compression ratio. Previous studies proposed techniques to dynamically enable compression to adapt to the program´s behavior. In the context of shared caches in multi-cores, the compression decision becomes more interesting because the cache is shared by multiple applications that may benefit differently from a compressed cache. This paper proposes Thread-Aware Dynamic Cache Compression (TADCC) to make better compression decisions on a per-thread basis. Access Time Tracker (ATT) can estimate the access latencies of different compression decisions. The ATT is supported by a Decision Switching Filter (DSF) that provides stability and robustness. As a result, TADCC outperforms a previously proposed adaptive cache compression technique by 8% on average and as much as 17%.
Keywords
cache storage; microprocessor chips; multiprocessing systems; access time tracker; decision switching filter; multicore processors; off-chip memory accesses; thread aware dynamic shared cache compression; Engines;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design (ICCD), 2011 IEEE 29th International Conference on
Conference_Location
Amherst, MA
ISSN
1063-6404
Print_ISBN
978-1-4577-1953-0
Type
conf
DOI
10.1109/ICCD.2011.6081388
Filename
6081388
Link To Document