High-level test generation for sequential circuits

An algorithm is presented for VLSI-circuit test-data transport at high levels of abstraction above gate-level. It can be used in the course of the test-pattern lift proposed by H. Hofestadt and M. Gerner (1987) for generating tests of sequential circuits. A precondition for its efficient use is a circuit under test without critical feedback cycles. Thus, an important aspect of the test strategy-the analysis of cycles in a sequential circuit-is proposed as a criterion for testability analysis. An efficient method for breaking critical feedback cycles is discussed. To minimize design-for-testability additions, the proposed approach uses inherently easily testable structures to a greater extent than conventional testing methods. The application of cycle analysis techniques and algorithm is demonstrated with the aid of a simple sequential circuit. Analysis shows that all circuit cycles could be recognized as noncritical