Title :
A study on relating redundancy removal in classical circuits to reversible mapping
Author :
Sultana, Sayeeda ; Radecka, Katarzyna ; Pang, Yu
Author_Institution :
Dept. of Electr. & Electron. Eng., McGill Univ., Montreal, QC, Canada
Abstract :
We present a way of synthesis of reversible circuits using redundant faults information obtained with the aid of its classical counterpart. We use Toffoli-based modules of classical standard gates and technology mapping to relate the effect of redundant stuck-at-value fault in classical irreversible gate level circuits and their reversible implementation. The simplified form of such Toffoli modules is proposed considering any fixed values of input signals (corresponding to stuck-at value effects). We also present redundant gates removal in reversible mapping.
Keywords :
fault diagnosis; logic circuits; logic gates; Toffoli-based module; classical irreversible gate level circuit; classical standard gate; redundant fault information; redundant gate removal; redundant stuck-at-value fault; relating redundancy removal; reversible circuit; reversible mapping; technology mapping; Automatic test pattern generation; Circuit faults; Fault diagnosis; Logic gates; Minimization; Redundancy; Wires; Reversible logic; redundancy removal; synthesis;
Conference_Titel :
Computer Design (ICCD), 2011 IEEE 29th International Conference on
Conference_Location :
Amherst, MA
Print_ISBN :
978-1-4577-1953-0
DOI :
10.1109/ICCD.2011.6081398
