Title :
Built-in self test using perturbed deterministic patterns
Author :
Wu, David M. ; Waicukauski, John
Author_Institution :
Dept. of Electr. Eng., Florida Inst. of Technol., Melbourne, FL, USA
Abstract :
A built-in self-test method that applies perturbed deterministic patterns (PDPs) generated by an on-chip memory and compresses signatures on-chip is presented. The deterministic patterns are perturbed using a predefined algorithm. Software and hardware implementation in a level-sensitive-scan design environment are described. Using six industrial benchmarks as examples, it is shown that the PDP test generator provides an equivalent or better test coverage than a deterministic test generator or a pseudorandom pattern generator. The number of patterns to be stored is much smaller than when using deterministic patterns, while the number of PDPs to be applied to the device under test is much smaller than when using pseudorandom patterns
Keywords :
VLSI; automatic testing; integrated circuit testing; integrated logic circuits; logic CAD; logic testing; VLSI; automatic testing; built-in self-test; industrial benchmarks; level-sensitive-scan design environment; logic CAD; on-chip memory; perturbed deterministic patterns; test generator; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Design for testability; Hardware; Linear feedback shift registers; Random number generation; Very large scale integration;
Conference_Titel :
European Test Conference, 1989., Proceedings of the 1st
Conference_Location :
Paris
Print_ISBN :
0-8186-1937-6
DOI :
10.1109/ETC.1989.36269
