Efficient pattern-based verification of connections to IP cores

Verification of designs containing pre-designed cores is a challenging topic in modern IC design. Traditional approaches generally do not use the information that parts of the design (like IP cores) are already verified. In this case, the verification of the IP core reduces to verifying the connectivity between the surrounding design and the core. Therefore, we propose a method that is based on test patterns. Using only those patterns for simulation, in almost all cases 100% of the errors can be detected. Existing test access logic is employed for the application of the patterns. A large set of experimental results is given to demonstrate the efficiency of the approach