A flexible logic BIST scheme and its application to SoC designs

Built-in self-test for logic circuits or logic BIST is an effective solution for the test cost, test quality, and test reuse problems. Logic BIST implements most ATE functions on chip so that the test cost can be reduced through less test time, less tester memory requirement, or a cheaper tester. Logic BIST applies a large number of test patterns so that more defects, either modeled or un-modeled, can be detected. In addition, logic BIST makes it easy to conduct the at-speed test for detecting timing-related defects. Furthermore, a BISTed- core makes SoC testing easier. Most of logic BIST schemes are based on the STUMPS structure, which applies random patterns generated by a PRPG to a full-scan circuit in parallel and compresses the responses into a signature with a MISR. The basic BIST flow includes initialization and a shift-capture loop. Logic BIST schemes are difficult to implement due to (1) potential timing violations at the borders from a PRPG to scan chains and from scan chains to a MISR, (2) potential timing problems caused by inserting test points, especially control points, (3) potential destructive shift operations due to clock glitches, and (4) potential overtests due to false paths activated by at-speed transition generation. This paper summarizes a flexible logic BIST scheme that addresses the above problems