DocumentCode :
2344459
Title :
AIG rewriting using 5-input cuts
Author :
Li, Nan ; Dubrova, Elena
Author_Institution :
ES/ICT, R. Inst. of Technol., Kista, Sweden
fYear :
2011
fDate :
9-12 Oct. 2011
Firstpage :
429
Lastpage :
430
Abstract :
Rewriting is a common approach to logic optimization based on local transformations. Most commercially available logic synthesis tools include a rewriting engine that may be used multiple times on the same netlist during optimization. This paper presents an And-Inverter graph (AIG) based rewriting algorithm using 5-input cuts. The best circuits are pre-computed for a subset of NPN classes of 5-variable functions. Cut enumeration and Boolean matching are used to identify replacement candidates. The presented approach is expected to complement existing rewriting approaches which are usually based on 4-input cuts. The experimental results show that, by adding the new rewriting algorithm to ABC synthesis tool, we can further reduce the area of heavily optimized large circuits by 5.57% on average.
Keywords :
logic circuits; logic design; 5-input cut; ABC synthesis tool; AIG rewriting; And-Inverter graph; Boolean matching; cut enumeration; logic optimization; logic synthesis; rewriting engine; Benchmark testing; Design automation; Field programmable gate arrays; Logic gates; Optimization; Runtime; USA Councils; Boolean matching; Logic optimization; NPN classes; cut enumeration; rewriting;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design (ICCD), 2011 IEEE 29th International Conference on
Conference_Location :
Amherst, MA
ISSN :
1063-6404
Print_ISBN :
978-1-4577-1953-0
Type :
conf
DOI :
10.1109/ICCD.2011.6081434
Filename :
6081434
Link To Document :
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