High speed dynamic MOS capacitor pull-up circuits

MOS capacitor pull-up circuits have been studied for high speed MOS digital circuits (1,2), where they are of interest because the output is derived on the leading edge of the clock pulse, with essentially instantaneous precharge by displacement current. The upper frequency limit has however in the past suffered from charge injection into the substrate (2). This paper will detail a successful solution to this problem, with experimental circuit confirmation and discussion of applications including timing circuits, fast decoding, and general logic. N-channel silicon gate integrated circuits realized to present have been a 10 bit serial to parallel shift register/ring counter, capable of driving capacitive loads off chip, and a 16 bit minimal area shift register. Operation on both has been achieved at 22 MHz (12 volt clocks), 18 MHz (8 volt clocks), 13 MHz (5 volt clocks) and 5 MHz (2 volt clocks). The paper will present (a) Results showing how with proper geometrical design and with substrate bias, charge injection to the source rather than to the substrate can be set up. (b) Measurements of the effects of injection to the substrate on circuit performance, when allowed to occur. (c) Some circuit configurations using capacitor pull-up, including fast decoders and an example realization of a moduloS counter.