Architecture of datapath-oriented coarse-grain logic and routing for FPGAs

In this paper, we propose a new datapath-oriented FPGA architecture that utilizes coarse-grain logic and routing resources to increase the area efficiency of datapath circuits. Using a set of custom-built datapath-oriented CAD tools and a set of datapath benchmarks, we investigated several variants of our proposed architecture. We found that the architecture achieves the highest area efficiency when 40% to 50% of the total routing tracks are coarse-grain. Furthermore, compared to conventional FPGA architectures, our datapath-oriented architecture uses about 10% less area to implement the same circuits.