Novel filled no-flow underfill materials and process

No-flow underfill has been invented and practiced in the industry for a few years. However, due to the interfering of silica fillers with solder joint formation, most no-flow underfills are not filled with silica fillers and hence have a high coefficient of thermal expansion (CTE), which is undesirable for high reliability. In a novel invention, a double-layer no-flow underfill is implemented to the flip-chip process and allows fillers to be incorporated into the no-flow underfill. The effects of bottom layer underfill thickness, bottom layer underfill viscosity, and reflow profile on the solder wetting properties are investigated in a design of experiment (DOE) using quartz chips. Silica fillers of different sizes and weight percentages are incorporated into the upper layer underfill. The process is implemented using CSP components and corresponding substrates. It is found that the thickness and viscosity of the bottom layer underfill are essential to the wetting of the solder bumps. With high viscosity bottom layer underfill, up to 40 wt% fillers can be added into the upper layer underfill and do not interfere with solder joint formation