The impact of wafer back surface finish on chip strength

Author

Lim, Thiam Beng

Author_Institution

Texas Instrum., Singapore Pte Ltd., Singapore

fYear

1989

fDate

11-13 Apr 1989

Firstpage

131

Lastpage

136

Abstract

A correlation between the wafer back surface roughness and the resistance of the chip to stress-induced failures is discussed. Chip strength was measured using the simply-supported beam method for chips of different backside roughness. Encapsulated samples were subsequently subjected to mechanical impact loading and thermal stresses as in vapor phase flow. The results show that the chip strength bears an inversely proportional relationship with the roughness of the wafer back. Hence, it is important to control the wafer back surface roughness for reliability improvement, especially for surface mount devices

Keywords

circuit reliability; encapsulation; failure analysis; impact testing; integrated circuit testing; monolithic integrated circuits; surface mount technology; surface topography; surface treatment; chip strength; encapsulated samples; mechanical impact loading; reliability; simply-supported beam method; stress-induced failures; surface mount devices; surface roughness; thermal stresses; vapor phase flow; wafer back surface finish; Assembly; Residual stresses; Rough surfaces; Semiconductor device measurement; Silicon; Surface cracks; Surface finishing; Surface resistance; Surface roughness; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 1989. 27th Annual Proceedings., International

Conference_Location

Phoenix, AZ

Type

conf

DOI

10.1109/RELPHY.1989.36334

Filename

36334