DocumentCode
2345041
Title
A 16-bit, 5MHz multi-bit sigma-delta ADC using adaptively randomized DWA
Author
Park, Yong-In ; Karthikeyan, S. ; Koe, Wem Ming ; Jiang, Zhongnong ; Tan, Tiak-Chean
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
2003
fDate
21-24 Sept. 2003
Firstpage
115
Lastpage
118
Abstract
This paper describes a 16 bit, 5 MHz analog to digital converter (ADC) chip that advances the state of the art of high speed sigma-delta ADCs by achieving a maximum output data rate of 5 MHz (2.5 MHz input signal bandwidth). The chip, which includes a novel multi-bit digital to analog converter linearization algorithm (AR-DWA) and an on-chip digital decimation filter, gives peak SNR, SFDR, THD of 88.5 dB, 106 dB, -103 dB, respectively.
Keywords
digital filters; integrated circuit design; linearisation techniques; sigma-delta modulation; 2.5 MHz; 5 MHz; AR-DWA; DAC linearization algorithm; SFDR; SNR; THD; adaptively randomized DWA; analog to digital converter; high speed ADC; input signal bandwidth; maximum output data rate; multi-bit ADC; on-chip digital decimation filter; sigma-delta ADC; Delta-sigma modulation; Integrated circuit noise; Logic; Multi-stage noise shaping; Noise cancellation; Noise shaping; Quantization; Sampling methods; Signal resolution; Signal to noise ratio;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN
0-7803-7842-3
Type
conf
DOI
10.1109/CICC.2003.1249372
Filename
1249372
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