DocumentCode
2345046
Title
p-MOSFET gate current and device degradation
Author
Ong, Tong-Chern ; Seki, Koichi ; Ko, Ping K. ; Hu, Chenming
Author_Institution
Intel Corp., Santa Clara, CA, USA
fYear
1989
fDate
11-13 Apr 1989
Firstpage
178
Lastpage
182
Abstract
Hot-carrier-limited device lifetime of surface-channel p-MOSFETs is found to correlate well with gate current over a wide range of bias. The same result is not observed for buried-channel p-MOSFETs. A gate current model for surface-channel p-MOSFETs is presented. Using this gate current model, reasonable estimates of AC stress lifetime can be made based on DC stress data
Keywords
hot carriers; insulated gate field effect transistors; life testing; semiconductor device models; semiconductor device testing; AC stress lifetime; DC stress; device degradation; gate current; hot carrier limited device lifetime; model; surface-channel p-MOSFETs; Degradation; Electron traps; Hot carrier effects; Hot carriers; Life estimation; Lifetime estimation; MOSFET circuits; Monitoring; Neodymium; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 1989. 27th Annual Proceedings., International
Conference_Location
Phoenix, AZ
Type
conf
DOI
10.1109/RELPHY.1989.36341
Filename
36341
Link To Document