DSP Algorithm Implementation of Synchronization and Frequency Offset Estimation for IEEE 802.16e Downlink

This paper presents synchronization and frequency offset estimation of IEEE 802.16e downlink implementation using preamble on digital signal processor. We considered time division duplex mode, physical layer base band processing, to detect the preamble and further calculate the symbol timing, frequency/phase offset and frame synchronization of the received signal. Consequent information of cell identification such as preamble index, ID cell and segment used can be deduced from detected preamble start symbol. In this paper, we further described a software implementation of the downlink transceiver function on Ten silica LX3 DSP. Numerical profiled data presented indicate the areas where further improvement can be investigated.