Title :
Scaling beyond the 65 nm node with FinFET-DGCMOS
Author :
Nowak, E.J. ; Ludwig, T. ; Aller, I. ; Kedzierski, J. ; Leong, M. ; Rainey, B. ; Breitwisch, M. ; Gemhoefer, V. ; Keinert, J. ; Fried, D.M.
Author_Institution :
IBM Syst. Group, IBM Microelectron. Div., Essex Junction, VT, USA
Abstract :
Exponential growth in leakage power density with physical scaling is driving ULSI technology towards innovative device architectures. Double-gate CMOS (DGCMOS), achieved through use of the Delta Device (D.Hisamoto et al, IEDM 1989, p.833-836), or FinFET (X.Huang et al, IEDM 1999, p.67-70), provides both a tactical solution to the gate-leakage challenge and a strategic scaling advantage. FinFET fabrication is very close to that of the conventional CMOS process, with only minor disruptions, yielding the potential for a rapid deployment to manufacturing. Planar circuit designs have been converted to FinFET-DGCMOS without disruption to physical area.
Keywords :
CMOS integrated circuits; ULSI; leakage currents; nanoelectronics; 65 nm; CMOS process; Delta Device; FinFET-DGCMOS planar circuit designs; ULSI technology scaling; double-gate CMOS; gate-leakage; leakage power density; CMOS process; CMOS technology; Clocks; Double-gate FETs; Fabrication; FinFETs; Frequency; Microelectronics; Subthreshold current; Ultra large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN :
0-7803-7842-3
DOI :
10.1109/CICC.2003.1249415
