Title :
Design and modeling challenges for 90 NM and 50 NM
Author :
Gerousis, Vassilios
Author_Institution :
Infineon Technol., Munich, Germany
Abstract :
This paper provides a description on specific design challenges at the 90 nm node and below. These challenges include modeling issues such as timing, leakage problems, and temperature effects. This paper shows several examples in design and modeling to illustrate the problems that are facing the design community at 90 nm. Based on current experience, we show projections of what could be facing the community at the 50 nm node.
Keywords :
integrated circuit design; integrated circuit modelling; leakage currents; low-power electronics; nanoelectronics; timing; 50 nm; 90 nm; IC design; IC modeling; leakage problems; low power circuits; low voltage circuits; nanoelectronics; temperature effects; timing; Crosstalk; Dielectrics and electrical insulation; Leakage current; Libraries; Low voltage; Semiconductor device modeling; Space technology; Temperature; Threshold voltage; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN :
0-7803-7842-3
DOI :
10.1109/CICC.2003.1249417
