The NAPA adaptive processing architecture

Author

Rupp, Charle R. ; Landguth, Mark ; Garverick, Tim ; Gomersall, Edson ; Holt, Harry ; Arnold, Jeffrey M. ; Gokhale, Maya

Author_Institution

Nat. Semicond. Corp., USA

fYear

1998

fDate

15-17 Apr 1998

Firstpage

28

Lastpage

37

Abstract

The National Adaptive Processing Architecture (NAPA) is a major effort to integrate the resources needed to develop teraops class computing systems based on the principles of adaptive computing. The primary goals for this effort include: (1) the development of an example NAPA component which achieves an order of magnitude cost/performance improvement compared to traditional FPGA based systems, (2) the creation of a rich but effective application development environment for NAPA systems based on the ideas of compile time functional partitioning and (3) significantly improve the base infrastructure for effective research in reconfigurable computing. This paper emphasizes the technical aspects of the architecture to achieve the first goal while illustrating key architectural concepts motivated by the second and third goals

Keywords

field programmable gate arrays; parallel architectures; reconfigurable architectures; FPGA based systems; NAPA adaptive processing architecture; National Adaptive Processing Architecture; application development environment; compile time functional partitioning; cost/performance improvement; teraops class computing systems; Application software; Clocks; Computer architecture; Computer interfaces; Field programmable gate arrays; Logic arrays; Parallel processing; Pipelines; Reconfigurable logic; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-8186-8900-5

Type

conf

DOI

10.1109/FPGA.1998.707878

Filename

707878