Title :
Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories
Author :
Pagiamtzis, Kostas ; Sheikholeslami, Ali
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Ont., Canada
Abstract :
This paper presents a pipelined match-line and a hierarchical search-line architecture to reduce power in content-addressable memories (CAM). The overall power reduction is 60%, with 29% contributed by the pipelined match-lines and 31% contributed by the hierarchical search-lines. This proposed architecture is employed in the design of a 1024×144 bit ternary CAM, achieving 7 ns search cycle time at 2.89 fJ/bit/search in a 0.18 μm CMOS process.
Keywords :
CMOS memory circuits; content-addressable storage; low-power electronics; pipeline processing; 0.18 micron; 147456 bit; 7 ns; CMOS; content-addressable memories; hierarchical search-line architecture; low-power CAM; pipelined match-line architecture; power reduction; ternary CAM search cycle time; CADCAM; CMOS process; Computer aided manufacturing; Computer architecture; Data compression; Databases; Energy consumption; IP networks; Pipelines; Power dissipation;
Conference_Titel :
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN :
0-7803-7842-3
DOI :
10.1109/CICC.2003.1249423
