DocumentCode
2346063
Title
A 16-bit, 20MSPS CMOS pipeline ADC with direct INL detection algorithm
Author
Hisano, Shinichi ; Sapp, Scott E.
Author_Institution
Fairchild Semicond., Colorado Springs, CO, USA
fYear
2003
fDate
21-24 Sept. 2003
Firstpage
417
Lastpage
420
Abstract
A 16-bit, 20 MSPS, 5 V pipeline ADC is implemented on a double poly, triple metal 0.5 μm CMOS process with a digital calibration algorithm that directly detects INL of MDACs. The measured INL and DNL are +3.5/-2.0 LSBs and ±0.6 LSBs, respectively. For a 5 MHz full scale input at 20 MSPS, it achieves 78 dB SNR and 91dB SFDR, consuming 750 mW. The die size is 6.23 mm×7.22 mm.
Keywords
CMOS integrated circuits; analogue-digital conversion; calibration; pipeline processing; 0.5 micron; 5 MHz; 5 V; 6.23 mm; 7.22 mm; 750 mW; CMOS; CMOS pipeline ADC; SFDR; SNR; digital calibration algorithm; direct INL detection; multiplying DAC integral nonlinearity; Calibration; Capacitance; Capacitors; Clocks; Decoding; Detection algorithms; Finite wordlength effects; Phased arrays; Pipelines; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN
0-7803-7842-3
Type
conf
DOI
10.1109/CICC.2003.1249431
Filename
1249431
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