Title :
A new characterization of sub-μm parallel multilevel interconnects and its experimental verification
Author :
Aoyama, Kimiko ; Ise, Kiyoshi ; Sato, Hisako ; Tsuneno, Katsumi ; Masuda, Hiroo
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
This paper describes a new interconnect design and its verification with test-structures for sub-micron multilevel interconnection. A universal design-chart has been developed, which gives a precise sub-micron interconnect-capacitance for parallel multilevel interconnections. Test-structure measurements show excellent agreement with the design-chart within 4% error. A simple propagation delay model has also been developed
Keywords :
capacitance; delays; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit testing; characterization method; interconnect capacitance; interconnect design; parallel multilevel interconnections; propagation delay model; submicron parallel multilevel interconnects; test structures; universal design chart; Application specific integrated circuits; Capacitance; Circuit optimization; Coupling circuits; Delay; Dielectric substrates; Integrated circuit interconnections; Testing; Transmission lines; Wiring;
Conference_Titel :
Microelectronic Test Structures, 1995. ICMTS 1995. Proceedings of the 1995 International Conference on
Conference_Location :
Nara
Print_ISBN :
0-7803-2065-4
DOI :
10.1109/ICMTS.1995.513946
