Reliability evaluation of thin gate oxide using a flat capacitor test structure

Author

Katsumata, M. ; Mitsuhashi, J. ; Kobayashi, K. ; Mashiko, Y. ; Koyama, H.

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan

fYear

1995

fDate

22-25 Mar 1995

Firstpage

103

Lastpage

106

Abstract

A test structure with very low-level current measurement technique (minimum detectable current is 5×10^-17 A) has been developed and is used for measuring very small change of leakage current caused by trapping and detrapping of electrons or holes. The present technique to measure very low level current of aA order is very useful for accurate evaluation of retention characteristics and stress induced degradation of gate oxide

Keywords

DRAM chips; EPROM; MOS capacitors; MOS memory circuits; electric current measurement; electron traps; hole traps; integrated circuit reliability; integrated circuit testing; leakage currents; silicon compounds; DRAMs; EEPROMs; MOS integrated circuits; SiO₂; detrapping; electron trapping; flat capacitor test structure; gate oxide; hole trapping; leakage current; low-level current measurement technique; reliability evaluation; retention characteristics; stress induced degradation; Bonding; Current measurement; Dielectric measurements; EPROM; Instruments; Leak detection; Leakage current; MOS capacitors; Stress measurement; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1995. ICMTS 1995. Proceedings of the 1995 International Conference on

Conference_Location

Nara

Print_ISBN

0-7803-2065-4

Type

conf

DOI

10.1109/ICMTS.1995.513954

Filename

513954