DocumentCode
2346721
Title
Specifying and compiling applications for RaPiD
Author
Cronquist, Darren C. ; Franklin, Paul ; Berg, Stefan G. ; Ebeling, Carl
Author_Institution
Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
fYear
1998
fDate
15-17 Apr 1998
Firstpage
116
Lastpage
125
Abstract
Efficient, deeply pipelined implementations exist for a wide variety of important computation-intensive applications, and many special-purpose hardware machines have been built that take advantage of these pipelined computation structures. While these implementations achieve high performance, this comes at the expense of flexibility. On the other hand, flexible architectures proposed thus far have not been very efficient. RaPiD is a reconfigurable pipelined datapath architecture designed to provide a combination of performance and flexibility for a variety of applications. It uses a combination of static and dynamic control to efficiently implement pipelined computations. This control, however, is very complicated; specifying a computation´s control circuitry directly would be prohibitively difficult. This paper describes how specifications of a pipelined computation in a suitably high-level language are compiled into the control required to implement that computation in the RaPiD architecture. The compiler extracts a statically configured datapath from this description, identifies the dynamic control signals required to execute the computation, and then produces the control program and decoding structure that generates these dynamic control signals
Keywords
decoding; field programmable gate arrays; formal specification; reconfigurable architectures; RaPiD; computation-intensive applications; control program; decoding structure; deeply pipelined implementations; dynamic control signals; flexible architectures; pipelined computation structures; reconfigurable pipelined datapath architecture; special-purpose hardware machines; statically configured datapath; Application software; Circuits; Computer applications; Computer architecture; Computer science; Decoding; Hardware; High level languages; Pipelines; Program processors;
fLanguage
English
Publisher
ieee
Conference_Titel
FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on
Conference_Location
Napa Valley, CA
Print_ISBN
0-8186-8900-5
Type
conf
DOI
10.1109/FPGA.1998.707889
Filename
707889
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