Resonant clocking using distributed parasitic capacitance

Author

Drake, Alan J. ; Nowka, Kevin J. ; Nguyen, Tuyet Y. ; Burns, Jeffrey L. ; Brown, Richard B.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

647

Lastpage

650

Abstract

A resonant clock distribution scheme that dissipates less power than conventional, buffer-driven clock distribution is described. All clock buffers are removed and the clock energy is resonated between integrated inductors and the parasitic capacitance of the local clock network, which form the energy storage elements of an LC VCO. Designed and fabricated in IBM´s 0.13 μm partially-depleted SOI, measurements show that the resonant clock dissipates 63% less power than a conventional, buffer-driven clock driving the same clock network.

Keywords

RLC circuits; circuit resonance; clocks; logic design; low-power electronics; silicon-on-insulator; voltage-controlled oscillators; 0.13 micron; LC VCO energy storage elements; RLC circuit; Si-SiO₂; buffer-driven clock distribution; clock energy reduction; distributed parasitic capacitance; integrated inductors; partially-depleted SOI; resonant clock distribution scheme; resonant clocking; Circuits; Clocks; Frequency; Inductors; Latches; Microprocessors; Parasitic capacitance; Resonance; Voltage-controlled oscillators; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249479

Filename

1249479