Design challenges for system-in-package vs system-on-chip

System-in-package (SiP) or multi-technology designs, as seen from a semiconductor industry point of view, have created a new set of design challenges. SiP designs are typically only attempted when a wall is reached -such as size or performance constraints and conventional system-on-chip (SoC) solutions are too expensive to implement. SoC involves accessing and working with one design/technology library and partitioning decisions are highly dependent on the library construction and routing capabilities that are identified within the software. The higher integration capacity of SiP reduces the number of components in the system and reduces the size and routing complexity of the printed circuit board. SiP design challenges arise due to the lack of similar design infrastructure between semiconductor technologies and the multitude of layout possibilities. Packaging concepts include chip stacked on chip, flip chip stacked on chip, chips placed side by side in a package, among other concepts which complicate the design partitioning process. This paper discusses these challenges to optimizing system design.