Digital beamforming techniques and processors based on quadratic residue number system techniques

A very-high-performance digital beamforming processor has been implemented using ASICs (application-specific integrated circuits) fabricated in readily available commercial CMOS process technology by using QRNS (quadratic residue number system) techniques. The chips have been designed and tested to operate at 50 MHz. The brassboard processor is capable of providing either four simultaneous beams, each with a bandwidth of 20 MHz, or 32 simultaneous beams, each with a bandwidth of 2 MHz. The brassboard system is capable of supporting 64 channels of 9-b I and 9-b Q digitized data and weights, but the architecture can support up to 512 channels of 14-b I and 14-b Q digitized data and weights. This demonstrates the feasibility of digital beamforming using silicon technology