Mismatch characterization of small size MOS transistors

Author

Bastos, J. ; Steyaert, M. ; Roovers, R. ; Kinget, P. ; Sansen, W. ; Graindourze, B. ; Pergoot, A. ; Janssens, E.R.

Author_Institution

ESAT, Katholieke Univ., Leuven, Heverlee, Belgium

fYear

1995

fDate

22-25 Mar 1995

Firstpage

271

Lastpage

276

Abstract

A test chip for characterization of transistor mismatch in a standard 1.2 μm CMOS technology is presented. A new algorithm for matching parameter extraction has been used. Mismatch parameters based on measurements on 12000 nMOS and 10000 pMOS transistors have been extracted. It is observed that the threshold voltage mismatch linear dependency on the inverse of the square root of the effective channel area no longer holds for transistors of 1.2 μm channel length. An extended model based on the physical causes of threshold voltage mismatch is proposed

Keywords

CMOS analogue integrated circuits; MOSFET; carrier mobility; integrated circuit testing; semiconductor device models; 1.2 micron; CMOS technology; channel length; device models; effective channel area; linear dependency; mismatch characterization; parameter extraction; small size MOS transistors; test chip; threshold voltage mismatch; transistor mismatch; CMOS technology; Erbium; MOS devices; MOSFETs; Packaging; Parameter extraction; Semiconductor device measurement; Size measurement; Testing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1995. ICMTS 1995. Proceedings of the 1995 International Conference on

Conference_Location

Nara

Print_ISBN

0-7803-2065-4

Type

conf

DOI

10.1109/ICMTS.1995.513986

Filename

513986