Code compression for the embedded ARM/THUMB processor

Author

Xu, Xianhong ; Jones, Simon

Author_Institution

Fac. of Eng. & Design, Univ. of Bath

fYear

2003

fDate

8-10 Sept. 2003

Firstpage

31

Lastpage

35

Abstract

Previous code compression research on embedded systems was based on typical RISC instruction code. THUMB from ARM Ltd is a compacted 16-bits instruction set showing a great code density than its original 32-bits ARM instruction. Our research shows that THUMB code is compressible and a further 10-15% code size reduction on THUMB code can be expected using our proposed new architecture - code compressed THUMB processor. In our proposal, level 2 cache or additional RAM space is introduced to serve as the temporary storage for decompressed program blocks. A software implementation of the architecture is proposed and we have implemented a software prototype based on ARM922T processor, which runs on the ARMulator

Keywords

cache storage; data compression; embedded systems; instruction sets; reduced instruction set computing; software prototyping; ARM922T processor; ARMulator; RISC instruction code; cache memory; code compression; embedded THUMB processor; reduced instruction set computing; software prototype; Arithmetic; Cache memory; Compression algorithms; Electronic equipment testing; Image coding; Instruction sets; Thumb; Timing; USA Councils;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2003. Proceedings of the Second IEEE International Workshop on

Conference_Location

Lviv

Print_ISBN

0-7803-8138-6

Type

conf

DOI

10.1109/IDAACS.2003.1249510

Filename

1249510