Title :
Clock switching: a new design for current testability (DcT) method for dynamic logic circuits
Author :
Rosing, Richard ; Richardson, Andrew M D ; Aimine, Yassine Eben ; Kerkhoff, Hans G. ; Acosta, Antonio J.
Author_Institution :
Microelectron. Res. Group, Lancaster Univ., UK
Abstract :
Using an Iddq test methodology on circuits with dynamic logic tends to be problematic, mainly due to charge leakage related problems. A new Design for current Testability (DcT) method has been developed, which overcomes these problems by switching the circuit into a static mode during test. The method referred to as clock switching is applicable to both domino logic and True Single-Phase Clock (TSPC) circuits. This paper shows that this technique can lead to higher levels of Iddq testability and a reduced test vector set for the detection of bridging faults
Keywords :
CMOS logic circuits; design for testability; integrated circuit testing; logic design; logic testing; switching; DFT; Iddq test methodology; IDDQ testability; TSPC circuits; bridging faults detection; clock switching; design for current testability; domino logic; dynamic logic circuits; static mode; test vector set reduction; true single-phase clock circuits; Circuit faults; Circuit testing; Clocks; Discrete cosine transforms; Frequency; Logic circuits; Logic testing; Performance evaluation; Switching circuits; Threshold voltage;
Conference_Titel :
IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-9191-3
DOI :
10.1109/IDDQ.1998.730727
