Title :
Model-based IDDQ pass/fail limit setting
Author :
Unni, T. Aruna ; Walker, D.M.H.
Author_Institution :
Xilinx Inc., San Jose, CA, USA
Abstract :
This paper describes several methods for setting LDDQ pass/fail limits using cell-based process, circuit and logic simulation. We demonstrate trade-offs in accuracy and model building effort on the ISCAS85 circuits
Keywords :
CMOS digital integrated circuits; circuit simulation; integrated circuit testing; logic simulation; logic testing; probability; CMOS ICs; IDDQ testing; ISCAS85 circuits; cell-based process; circuit simulation; dynamic method; logic simulation; model-based IDDQ pass/fail limit setting; probability method; worst case method; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Drives; Logic circuits; Production; Semiconductor device modeling; Switches; Temperature;
Conference_Titel :
IDDQ Testing, 1998. Proceedings. 1998 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-9191-3
DOI :
10.1109/IDDQ.1998.730731
