Title :
Robust design of sub-threshold flip-flop cells for wireless sensor network
Author :
Jin, Wei ; Lu, Sheng ; He, Weifeng ; Mao, Zhigang
Author_Institution :
Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China
Abstract :
As a major sequential logic element, D flip-flop is an indispensible cell in logic cell library. In this paper, we proposed two improved sub-threshold D flip-flop circuits (mTGMS and emC2MOS D flip-flop) after conducting robustness analysis of several typical flip-flop circuits. Using SMIC 0.18um CMOS technology, the simulation results show that the minimum work voltage of our proposed mTGMS and emC2MOS is 0.19V and 0.18V, the minimum average power is 13.2pW and 14.1pW, while the minimum Power Delay Product (PDP) is 13aJ and 4.35aJ respectively.
Keywords :
CMOS logic circuits; flip-flops; sequential circuits; wireless sensor networks; SMIC CMOS technology; emC2MOS; energy 13 aJ; energy 4.35 aJ; logic cell library; mTGMS; major sequential logic element; minimum PDP; minimum average power; minimum power delay product; power 13.2 pW; power 14.1 pW; robustness analysis; size 0.18 mum; subthreshold D flip-flop circuit; voltage 0.18 V; voltage 0.19 V; wireless sensor network; Clocks; Delay; Flip-flops; Inverters; Logic gates; Multiplexing; Robustness; D flip-flop; sub-threshold circuit; ultra-low power;
Conference_Titel :
VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4577-0171-9
Electronic_ISBN :
978-1-4577-0169-6
DOI :
10.1109/VLSISoC.2011.6081623
