Design-for-Iddq-testing for embedded cores based system-on-a-chip

System-on-a-chip (SoC) ICs in deep submicron technologies present major challenges in the implementation of Iddq testing. The problems are increased leakage current due to increasing number of gates as well as due to increased sub-threshold leakage of the individual transistors. While methods such as substrate-bias and low temperature are adequate to reduce sub-threshold leakage in deep submicron technologies, almost no solution is available to address the issue of increased leakage due to enormous size of the SoC design. In this paper, we first present a design-for-test concept to address the issue of high leakage due to the large size of SoC design. Secondly, we provide some design rules that are necessary to make SoC design suitable for Iddq testing. The design methodology presented in this paper facilitates Iddq testing by controlling power-supply of the individual cores through JTAG boundary scan and allows Iddq testing on one core at a time. The design does not require any dedicated pin for this control and area overhead is negligible