Hardware Implementation of Advanced Encryption Standard

Advanced Encryption Standard, a federal information processing standard is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. However field programmable gate array offers a quicker and more customizable solution. This paper presents the AES algorithm with regard to FPGA and the very high speed integrated circuit hardware description language. Modelsim SE PLUS 5.7g soft ware is used for simulation and optimization of the synthesizable VHDl code. Synthesizing and implementation of the code carried out on Xilinx -project navigator, ISE 8.2i suite. All the transformations of both encryption and decryption are simulated using an iterative design approach in order to minimize consumption. This paper talks of AES 128 bit block and 128 bit cipher key and is implemented on Spartan 3 FPGA.