Exploiting maximum throughput in 3D multicore architectures with stacked NUCA cache

Demands for high performance are growing rapidly and multiple processor cores and huge caches are required to meet these requirements. 3D integration provides us a very bright option to encounter this by integrating numerous cores and cache layers in a single chip. Temperature however becomes a problem in 3D integration due to increased power density. A methodology to exploit maximum performance while keeping the temperature under a given limit has been proposed in this paper. We have solved for the optimum clock frequencies, cache capacity and the placement of cache banks for each core to get the maximum throughput. Experiments are done on multiple benchmark programs and a peak 53% and an average 49% improvement in performance as compared to the base case which assigns same frequency and number of banks to each core is found.