Early planning for RT-level delay insertion during clock skew-aware register binding

In current VLSI complexity systems, clock skew scheduling is one of the key approaches to improve circuit performance and reliability. A delay insertion method has been discussed in logic-level to reduce the clock period. This paper extends this idea into high-level synthesis (HLS), and introduces a new HLS task, namely the minimum-path delay assignment. Since register binding plays an important role on the effect of the minimum-path delay assignment, this paper formulates the problem of simultaneously optimizing register binding and the minimum-path delay assignment. An MILP-based approach will be presented, and evaluated by experiment which shows the approach can reduce the clock period with an average of 14.1% compared to conventional clock skew-aware design.