DocumentCode :
2348655
Title :
New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory
Author :
Ming, Zhu ; Yi, Xiao Li ; Wei, Luo Hong
Author_Institution :
Microelectron. Center, Harbin Inst. of Technol., Harbin, China
fYear :
2011
fDate :
3-5 Oct. 2011
Firstpage :
254
Lastpage :
259
Abstract :
Nowadays, multiple bit upsets (MBUs) have been widely investigated in memories. Conventional single error correction and double error detection (SEC-DED) codes are capable of correcting one error and detecting all possible double errors. However, they may not provide adequate protection against MBUs. This paper proposes new single-error-correction, double-error-detection double-adjacent-error-correction (SEC-DED-DAEC) codes to mitigate radiation or noise source induced MBUs in memories. The proposed SEC-DED-DAEC codes are obtained from conventional SEC-DED codes according to the mathematics model established in this paper. They can detect and correct all adjacent double bit errors and assure a lower miscorrection probability for non-adjacent double bit errors compared with other SEC-DED-DAEC codes. Furthermore, the redundancy bits of the proposed scheme are the same as those of conventional SEC-DED codes. This means that the increase of correct-capability do not cause additional hardware overhead for the memory system. Finally, the experiment results reveal that the proposed scheme reduces the miscorrection probability of non-adjacent double bit errors by 12% compared to the best known SEC-DED-DAEC codes. Moreover, compared to the well known BCH codes, the proposed scheme reduces 40% hardware redundancy and keeps an acceptable reliability.
Keywords :
error correction codes; storage management chips; MBU; SEC-DED-DAEC codes; double error detection codes; double-adjacent-error-correction codes; memory system; multiple bit upsets mitigation; noise source; single error correction codes; Decoding; Equations; Logic gates; Mathematical model; Reliability; Vectors; MBUs; SEC-DED-DAEC codes; memory; memory reliability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4577-0171-9
Electronic_ISBN :
978-1-4577-0169-6
Type :
conf
DOI :
10.1109/VLSISoC.2011.6081647
Filename :
6081647
Link To Document :
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