Integration study of die strength and various bumping volume and reliability performance on 2.5D silicon interposer assembly

The applications of 2.5D/3D IC integration have been increasing in recent years, which enable high-density and heterogeneous ICs that can be assembled in one package using through silicon interposer (TSI). In this paper, the integration study of interposer in backside via reveal (BVR) process, various bumping volume and stacking reliability were introduced. Different sizes of solder bump forms on the same side of interposer may become essential in order to reduce not only package parasitic and shorten the interconnection length but also can be developed to cost down for equal IC packaging performance in any kind of 2.5D system packaging. The proposed electrical plating solder bump with different size for top functional dies attachment. This technique shortens overall process time in manufacturing because it provides simpler and shorter total amount of process steps. We studies high volume and low volume solder bump with logic circuit and memory integrated on silicon interposer. The result shows electrical function is feasible. The interposer BVR process makes die strength reduction while wafer thickness reduced and nitride film covered, It is found that grinding degrades strength significantly if surface is rougher; the chemical vapor deposition(CVD) passive film makes interposer structure as a composite material and dropped die strength significantly from dozen kilogram to hundreds gram level; in further processing, the chemical mechanical planarization(CMP) and C4 bumping will reduce strength a lot about 10 times from several kilogram to hundreds gram level. The strength enhancement were experimentally studied in terms of grinding optimization to control roughness under 1nm; the various kinds of CVD film were deposited; then CMP experiments added. Finally, we gain 2~3 times of die strength totally. The stacking process scenario: Chip on Chip first (CoC first) was evaluated by various 2.5D assembly structure. The process flow that active dies are mounted on TSI fi- stly and then the CoC module is mounted on organic substrate is more practicable and reliable. The evaluations were experimentally studied in terms of warpage and thermo-mechanical stress and finally demonstrated the CoC first process flow is more reliable to assure high assembling yield. The robustness of 3D integrated package was also evaluated by QTC (Quick Temperature Cycle) test and the result showed low stress of passive film of TSI promised superior solder joint performance during tests. The package reliability tests were further conducted in terms of preconditioning (MSL-4), THT (Temperature Humidity Testing), un-biased HAST (Highly Accelerated Stress Testing), HTST (High Temperature Storage Test) and TCT (Thermal Cycling Test). The O/S (Open/Short) test and C-SAM imaging were applied for these reliability tests to monitor package integrity. The ASIC-die 2.5D integrated packages have passed O/S test after preconditioning and 2000X TC-B test, no significant issues were found. Furthermore, most integrated samples have passed the other reliability tests such as THT 1000hrs, and HTST 1000hrs.