• DocumentCode
    234879
  • Title

    Large area interposer lithography

  • Author

    Flack, Warren ; Hsieh, Robert ; Kenyon, Gareth ; Ranjan, Manish ; Slabbekoorn, John ; Miller, Alice ; Beyne, Eric ; Toukhy, Medhat ; PingHung Lu ; Yi Cao ; Chunwei Chen

  • Author_Institution
    Ultratech Inc., San Jose, CA, USA
  • fYear
    2014
  • fDate
    27-30 May 2014
  • Firstpage
    26
  • Lastpage
    32
  • Abstract
    Large area silicon or glass interposers may exceed the maximum imaging field of step and repeat lithography tools. This paper discusses the lithographic process used to create a large area interposer on a stepper by the combination of multiple subfield exposures. Overlay metrology structures are used to confirm the relative placement of the subfields to construct the interposer. Routing lines from 1.5 to 4.0 μm in width are evaluated to measure critical dimension (CD) control where the lines cross the subfield boundaries. CD metrology at the bottom and top of the photoresist is performed using a top down CD-SEM. Finally large area test interposers are patterned using two subfields on a 1X stepper and processed through a Cu electroplating module for detailed characterization. The CD control of routing lines as they cross the subfield boundary can be optimized by using a shaped or tapered line end design. Lithography simulation using Prolith modeling software by KLA-Tencor is matched to experimental results and then used to evaluate performance of various line end designs. Larger latitude for overlap error was observed for the tapered line end compared to the standard square line end. The experimental and modeled results in this study show the capability of using stepper lithography to produce large area interposers with 1.5 μm I/O routing line dimensions.
  • Keywords
    copper alloys; electroplating; photolithography; photoresists; scanning electron microscopy; 1X stepper; CD control; Cu; I/O routing line dimensions; KLA-Tencor; Prolith modeling software; copper electroplating module; critical dimension control measurement; glass interposers; large area interposer lithography; large area silicon; large area test interposers; lithography simulation; maximum imaging field; multiple subfield exposures; overlap error; overlay metrology structures; photoresist; repeat lithography tools; routing lines; size 1.5 mum to 4.0 mum; standard square line end; step lithography tools; stepper lithography; subfield boundary; tapered line end design; top down CD-SEM; Layout; Lithography; Metals; Metrology; Resists; Routing; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
  • Conference_Location
    Orlando, FL
  • Type

    conf

  • DOI
    10.1109/ECTC.2014.6897262
  • Filename
    6897262