Performance Verification for Cache Memory of Multicore Processor

Author

Dhakad, Pradeep ; Katariya, Abhishek ; Arya, Antim

Author_Institution

Dept. of Electron. & Commun. Eng., Mandsaur Inst. of Technol., Mandsaur, Malaysia

fYear

2010

fDate

26-28 Nov. 2010

Firstpage

622

Lastpage

627

Abstract

The cache hierarchy design in existing SMT and a superscalar processor is optimized for latency, but not for bandwidth. The size of the Level 1 (L1) data cache did not scale over the Past decade. Instead, larger unified Level 2 (L2) and Level 3 (L3) caches were introduced. The present paper is the part of the L3 cache. This paper describes last level cache memory decoding structure, which is designed mainly to improve performance. Functional verification as well as pre layout and post layout STA and ERC verifications are done on the 4MB cache. Results of each verification flow are presented. Based on the SDP methodology, good placement and routing, RC extraction, and noise analysis are achieved. SDP methodology is proven better than the RLS methodology for data path configurations. Cadence tools are used for performing the verification of SDP flows.

Keywords

cache storage; integrated circuit layout; logic design; memory architecture; multi-threading; multiprocessing systems; ERC verification; RC extraction; RLS methodology; SDP methodology; STA verification; cache hierarchy design; cache memory; cadence tool; data path configuration; electrical rule check; layout synthesis; multicore processor; noise analysis; performance verification; register transfer logic; simultaneous multithreading; static timing analysis; structural data path; superscalar processor; Electrical Rule Check (ERC); Register Transfer Logic to Layout Synthesis (RLS); Resistance-Capacitance (RC); Simultaneous Multi Threading (SMT); Static Timing Analysis (STA); Structural Data Path (SDP);

fLanguage

English

Publisher

ieee

Conference_Titel

Computational Intelligence and Communication Networks (CICN), 2010 International Conference on

Conference_Location

Bhopal

Print_ISBN

978-1-4244-8653-3

Electronic_ISBN

978-0-7695-4254-6

Type

conf

DOI

10.1109/CICN.2010.123

Filename

5702046