Title :
Combinational logic synthesis for material implication
Author :
Chattopadhyay, Anupam ; Rakosi, Zoltan
Author_Institution :
MPSoC Archit., RWTH Aachen Univ., Aachen, Germany
Abstract :
The smooth scaling of technology over past decades is returning diminished profits as researchers are trying to cope with several challenges posed by CMOS devices. As a result, quest for novel physical media for storage and computing is currently an important research pursuit. Recently a new kind of passive electrical device called memristor is proposed, which can retain its state via the resistance in a non-volatile fashion. It is also experimentally demonstrated to perform material implication, a fundamental logical operation. The capability of a memristive device to do logical operations as well as to retain its state makes it a promising candidate for future technologies. In this paper, we investigate the approximate implementation cost of a multi-level combinational logic while using memristive switches as the target technology. Traditional synthesis algorithms are extended and new heuristics are suggested to reduce the costs significantly.
Keywords :
CMOS integrated circuits; combinational circuits; logic design; memristors; CMOS device; combinational logic synthesis; logical operation; material implication; memristive device; memristive switches; memristor; multilevel combinational logic; passive electrical device; physical media; DH-HEMTs;
Conference_Titel :
VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4577-0171-9
Electronic_ISBN :
978-1-4577-0169-6
DOI :
10.1109/VLSISoC.2011.6081665