Title :
A clock-less transceiver for global interconnect
Author :
Jiang, Jian-Fei ; Wang, Xu ; Sheng, Wei-Guang ; He, Wei-feng ; Mao, Zhi-gang
Author_Institution :
Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China
Abstract :
High speed and low power transceivers start to be used for global interconnection in state-of-the-art System-on-Chips (SoCs). In traditional transceivers, the bandwidth is largely dependent on the clock rate. This paper presents a clock-less transceiver for global interconnect. The asynchronous transceiver makes the data rate only depend on the link delay and can be conveniently used with low swing scheme to create a high speed and low power communication system. The transceiver is demonstrated and simulated. The simulation results indicate that the transceiver can be used in high speed and low power global communications.
Keywords :
logic design; radio transceivers; system-on-chip; SoC; asynchronous transceiver; clock-less transceiver; global interconnect; high speed transceiver; low power transceiver; system-on-chip; Delay; Encoding; Integrated circuit interconnections; Receivers; System-on-a-chip; Transceivers; Wires; asynchronous; interconnect; low power; low swing; transceiver;
Conference_Titel :
VLSI and System-on-Chip (VLSI-SoC), 2011 IEEE/IFIP 19th International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4577-0171-9
Electronic_ISBN :
978-1-4577-0169-6
DOI :
10.1109/VLSISoC.2011.6081672
